1. Field of the Invention
The present invention relates to an image display system and a display device, where the display device is coupled to a host device such that an image is displayed on the display device in accordance with an image signal which is output from the host device.
2. Description of the Related Art
Display devices which display images on a display in accordance with access signals (a video signal, a synchronization signal, etc.) which are regularly transmitted from a host device are known.
Such a display device maintains a so-called one-to-one “master-slave” relationship with a host device, where the host device is the master and the display device is the slave. In order to transfer images to a display device from a personal computer serving as a host device, one graphic controller (chip) is usually required for each display device as an interface with the host device.
In recent years, display systems have been proposed in which a personal computer serving as a host device is interconnected with a plurality of display devices. Such display devices maintain a one-to-many “master-slave” relationship with a host device, where the host device is the master and the display devices are the slaves. In such cases, it may be possible to provide in the personal computer a plurality of driving mechanisms for driving the display devices so that each display device is controlled by the personal computer.
However, it is often the case with usual interfaces that, as the number of display devices to be coupled increases, the system power and/or the graphic controller power decrease so that it becomes difficult to obtain a sufficient image displaying function.
In order to overcome the problem of inadequate graphic controller power, a method has been proposed which involves providing a memory in each one of a plurality of display devices which are coupled to a personal computer, and compromising (i.e., slowing down) the speed of transfer to a technically possible transfer rate. For example, during normal operation of displaying moving pictures on the display devices, display is performed while retaining (i.e., writing and reading) in a frame memory of each display device a video signal which is synchronized with a synchronization signal transmitted from the personal computer. When the transmission of the synchronization signal is interrupted, the writing to the frame memory is stopped, and display is performed while reading the information which is retained in the frame memory.
Next, power management of the aforementioned display systems will be discussed.
Power management f or conventional display devices is performed as follows. In the case where a one-to-one “master-slave” relationship exists between a host device and a display device, and the “slave” or the display device is to be turned OFF, the display device detects the presence or absence of a synchronization signal from the “master” or the host device. If it is determined that a synchronization signal is not being transmitted, the display device turns itself OFF. This conventional example will be described with reference to FIG. 3.
FIG. 3 is a block diagram illustrating a conventional image display system. This image display system includes a display controller section 1 as a host device (e.g., a personal computer), which drives a display section 2 implemented by using a display device such as a liquid crystal display (LCD).
The display controller section 1 includes a display control circuit 5, which is connected via a system bus 6 to a host system (not shown) that executes various applications. The display control circuit 5 is connected to a graphic memory 3 via a graphic memory bus 4. The display control circuit 5 is also connected to an image processing circuit 8 and a synchronization circuit 13 in the display section 2 via an interface bus 7. The image processing circuit 8 sends image data to a display circuit 12 via an image data bus 21. The synchronization circuit 13 sends a synchronization signal 14 to the display circuit 12.
FIG. 4 shows various signals which are sent through the interface bus 7. In FIG. 4, an image signal conveys information containing a video signal component; a data-enable signal is a signal which indicates an enabled period of the image signal; a synchronization signal is a signal which indicates the refresh timing for the image signal; and a data transfer clock is a sampling clock signal for transferring the image signal, the data-enable signal, and the synchronization signal.
Next, a flow of image data in the above image display system will be described.
The image signal which is transmitted from the host system (not shown) is first processed by the display control circuit 5 and the graphic memory 3 in the display controller section 1 serving as a host device, and thereafter is transmitted via the interface bus 7 to the image processing circuit 8 and the synchronization circuit 13 in the display section 2 along with the data-enable signal, the synchronization signal, and the data transfer clock signal. The signals which are transmitted through the interface bus 7 may have been subjected to analog and/or digital processing (such as multiplexing or compression) in accordance with the specification of any signal media used. The image processing circuit 8 processes the incoming data, and transmits an image component of the image signal to the display circuit 12. The synchronization circuit 13 processes the incoming data, and transmits the synchronization signal 14 to the display circuit 12. The display circuit 12 displays an image in accordance with the received image component of the image signal and the synchronization signal.
Next, power management for the display section 2 in the above image display system will be described. In the case where the host system (not shown) and the display controller section 1 are turned OFF, or where the display controller section 1 is in a sleep state, the transmission of the synchronization signal from the display controller section is stopped. The synchronization circuit 13 in the display section 2 detects the presence or absence of the synchronization signal from the display controller section 1 via the interface bus 7. Upon determining that a synchronization signal is not being transmitted, the display section 2 turns itself OFF.
However, there is a problem in that the aforementioned power management method for a display system including a host device and a display device under a one-to-one “master-slave” relationship (i.e., the display device detects the presence or absence of a synchronization signal from the “master” or the host device and turns itself OFF upon determining that a synchronization signal is not being transmitted) cannot be effectively used in a display system including a host device and a plurality of display devices under a one-to-many “master-slave” relationship, where display is performed while reading the information which is retained in a frame memory when the transmission of the synchronization signal is interrupted, during which time writing to the frame memory is stopped because it is impossible for each display device to administer its own power management.
The reason is that, in a display system including a host device and a plurality of display devices under a one-to-many “master-slave” relationship, the absence of a synchronization signal transmitted from a host device (which serves as a determination criterion in the conventional power management method for a display system under a one-to-one “master-slave” relationship) will be used not only as a marker for determining whether or not to allow the display device to turn itself off, but also as a marker for determining whether or not to switch to the mode of reading the information retained in a frame memory.